Cadence combines ML techniques for power signoff

Cadence Design Systems has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.

The company claims it is seeing a doubling in productivity in dealing with signoff violations using the Voltus InsightAI tool. One key element of the tool is the inclusion of an inference engine trained on numerous simulations to reduce the overall computational overhead that comes with computing the interactions across large power networks. The engine is used to internal models of the power grid that can perform incremental IR analysis to provide rapid feedback on the impact of design changes.

A second component is the use of deep-learning models to identify the likely causes of IR drop problems, identifying aggressors, victims, and resistance bottlenecks. Decision-tree methods are then used to perform timing and design rule check (DRC)-aware fixes of IR drop, selecting from changes such as placement, grid reinforcement, and routing alterations.

“As we move to more advanced nodes, EM-IR is quickly becoming one of the most pressing challenges, requiring novel and innovative approaches to address customer needs” said Ben Gu, corporate vice president of R&D in Cadence’s multiphysics systems analysis business unit. “With this capability, designers don’t need to over-design the power grid, thereby enabling far better PPA. Customers are seeing impressive results as they can leverage this technology to fix up to 95% of violations prior to signoff.”